The present invention relates, generally, to electrically-erasable-programmable-read-only-memory (EEPROM) devices and, more particularly, to improving the capacitive coupling within an EEPROM device.
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the EEPROM device. In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode that may be formed as a region in the substrate. The control-gate is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two transistor design or a three transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a sense transistor. In a two transistor device, the functions of read and sense transistors are combined into a single transistor. To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively high voltage Vpp is applied to the drain (bitline contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bitline to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bitline and a high voltage Vpp+ is applied to the control-gate. Under this bias condition, the high voltage applied to array-control-gate is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode.
Efficient programming of the EEPROM cell requires a large capacitive coupling between the floating gate electrode and the array-control-gate. Improved capacitive coupling also allows programming and erasing to be carried out at reduced voltages. Additionally, during the read cycle, improved reading currents can be achieved. The capacitive coupling is improved by increasing the capacitor area, which is typically accomplished by increasing the size of the floating gate electrode or substrate area of the array-control-gate, or both.
Although, simply increasing the area of the floating gate electrode or the array-control-gate improves capacitive coupling, the trend in PLD semiconductor fabrication is toward smaller, faster EEPROM cells that occupy little substrate area. Accordingly, a need exists for an EEPROM device and fabrication process to produce an EEPROM device having high capacitive coupling, while not requiring a corresponding increase in substrate area in which to build the device.
The present invention is for an EEPROM device with improved capacitive coupling and a process for fabricating the device. In accordance with the invention, a single-gate layer EEPROM device is provided having a high coupling ratio between the floating gate electrode and a control gate electrode residing in a semiconductor substrate in close proximity to the floating gate electrode. By forming a capacitor plate that at least partially overlies the floating gate electrode, a large capacitive coupling is obtained between the control gate and the floating gate. By providing a high capacity coupling, the substrate area required for the control gate can be reduced enabling the overall size of the EEPROM device to also be reduced.
In accordance with the invention there is provided a single-gate layer EEPROM device that includes a control gate region in a semiconductor substrate and a floating gate electrode overlying at least a portion of the control gate region and separated from the control gate region by a first capacitor dielectric layer. A second capacitor dielectric layer overlies the floating gate electrode and a capacitor plate at least partially encapsulates the floating gate electrode. The capacitor plate is locally interconnected to the control gate region.
In another aspect, the invention includes a process for fabricating a single-gate layer EEPROM device that includes providing a semiconductor substrate having a floating gate electrode overlying a control gate region and separated from the control gate region by a first capacitor dielectric layer. A second capacitor dielectric layer is formed to overlie the floating gate electrode and a salicide process is carried out to form a capacitor plate that encapsulates at least a portion of a floating gate electrode and a local interconnect is formed to electrically couple the salicide capacitor plate to the control gate region in the semiconductor substrate.